With the growing complexity of integrated systems such as SoCs (Systems on Package), the power management of the varied elements of such systems has become a crucial element of the system operation. In the power management of systems, one of the functions of the firmware and BIOS (Basic Input/Output System) generally is to shut down as many components of the system as possible to reduce power consumption, including shutdown in a reset sequence.
However, this shutdown operation during the reset sequence runs contrary to platform testing (also referred to as board-level testing) requirements, which require having as many components as possible to be enabled for accurate testing.
Among the elements that are shut down by power management are the clock elements for the system. When a platform test is enabled, the clocks supplied by the platform controller hub (PCH) thus have been disabled by the PCH platform testing chain. However, the shutdown of the clocking prevents implementation of reliable board level testing.